Means and method for disabling access to a memory
US4446475A · kind A · utility
28Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1981 |
| Grant date | May 1, 1984 |
| Priority date | — |
| Expiry date | Jul 10, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip having a digital memory is provided wherein direct access to at least a portion of the memory is prevented. Contact pads having coupling lines to couple the contact pads to the memory bus are provided. A security code can be programmed into a portion of the memory during wafer probe and test. When the integrated circuit chip is removed from the wafer the coupling lines between the contact pads and the memory bus are destroyed since the coupling lines are made to extend off of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.