Data processing systems with expanded addressing capability
US4449181A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1980 |
| Grant date | May 15, 1984 |
| Priority date | — |
| Expiry date | Oct 2, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to memory-mapping and protection facilities in multi-processor data-handling systems. A feature of the invention relates to systems in which a plurality of processors, including both arithmetic processors and processors for the control of external data handling devices, communicate with each other and with a main store using a shared data-bus. Addresses generated by the processors are split into a most significant part A and a least significant part B. The part A is used to address a table store which generates the most significant digits P of the main store address, with an indication Q of the type of access permitted (e.g. read only or read and write). The digits P and B serve to form the address of a main store location or a device control processor function, the digits Q being communicated with them over the data-bus and used to address in a controlled manner, main store locations and device control processor functions. In the preferred implementation the table store holds a large number (e.g. 64) of tables and a table number store holds, for each processor the number of the table currently in use. This enables processors to be allocated tables rapidly and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.