Binary MOS parallel comparators
US4450432A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1981 |
| Grant date | May 22, 1984 |
| Priority date | — |
| Expiry date | Aug 26, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The monolithic integrated binary MOS parallel comparator uses enhancement-mode insulated-gate field effect transistors of the same conductivity type and comprises n successively weighted stages each including a NOR block having at least two inputs each receiving a correspondingly weighted digit of a different one of a first and a second n-digit binary word and an additional logic circuit also receiving the correspondingly weighted digit of the first and second words, and an output logic circuit coupled to each of the n stages to provide an output signal for the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.