Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories
US4450519A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1980 |
| Grant date | May 22, 1984 |
| Priority date | — |
| Expiry date | Nov 24, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register (IR) with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-chip memory does not affect the off-chip main memory map. Microprocessors are thus made more versatile and can be customized with little design effort.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.