Distributed arithmetic digital processing circuit
US4450533A · kind A · utility
Inventors
Key dates
| Filing date | Aug 17, 1981 |
| Grant date | May 22, 1984 |
| Priority date | — |
| Expiry date | Aug 17, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0241
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital processing circuit forming a weighted sum of digital signals. It comprises n groups of M series registers (10/1, . . . , 10/nM) into which are introduced the signals to be processed, n multiplexers (15/1, 15/2, . . . , 15/n), a memory (20) containing precalculated quantities characteristic of the weighted sum to be formed, said memory having a capacity of 2 .sup..beta.+n words distributed into different blocks, a modulo M counter (25), an adder-subtracter (30) connected to the memory, an accumulator-register (40) connected to the adder-subtracter and a clock (50) actuating the counter and the registers. The circuit is in that the memory is subdivided into [M-(2.sup..beta. -M)] blocks of 2.sup.n words and into (2.sup..beta. -M) blocks of 2.sup.n+1 words, said blocks being selected by the bits supplied to the outputs of the counter, in that it comprises supplementary series registers, whose number is at the most equal to 2.sup..beta. -M, said series registers receiving the supplementary signals to be processed and in that it also comprises a multplexing means (21) controlled by the outputs of the counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.