Address buffer circuit with low power consumption
US4451745A · kind A · utility
18Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1980 |
| Grant date | May 29, 1984 |
| Priority date | — |
| Expiry date | Dec 8, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a latch-type address buffer circuit for use in a clock-synchronous CMIS.RAM, a transistor is connected between an inverter, which is supplied with an address signal and the power source. A clock circuit is provided for generating an internal clock signal by which only in the period of latching the input address signal, the transistor is turned ON to make the inverter operative, thus reducing the total power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.