Level detecting circuit
US4453091A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1982 |
| Grant date | Jun 5, 1984 |
| Priority date | — |
| Expiry date | Mar 23, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G7/002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level detecting circuit for use in a noise reduction circuit and which produces a level detected output signal in response to an input signal, includes an operational amplifier with at least one feedback diode for logarithmically converting the input signal to produce a logarithmically converted signal; a first PN junction element comprised of a first diode supplied with the logarithmically converted signal; a second PN junction element comprised of a second diode connected in series with the first diode at a connection point, the series-circuit of the first and second diodes having a first saturation current; a first integrating capacitor having a first capacitance and connected to the connection point for producing an integrated signal; a third PN junction element comprised of series-connected third and fourth diodes connected in parallel with the series connection of the first and second diodes and having a second saturation current greater than the first saturation current; a second integrating capacitor having a second capacitance less than the first capacitance and connected to the second and fourth diodes; a reference current source for providing a reference current to the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.