Comparator circuit having reduced input bias current
US4453092A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 1982 |
| Grant date | Jun 5, 1984 |
| Priority date | — |
| Expiry date | Dec 27, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2418
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator circuit which includes a differential pair of transistors forming differential inputs of the comparator and a voltage level shift circuit coupled in series connection path with the emitters of the pair of transistors. The voltage level shift circuit includes an additional transistor having its collector-emitter path connected in series between an output of the comparator and the emitter of the first pair of transistors; a first diode coupled a series-conduction path to the emitter of the second one of the pair of transistors and having an anode connected to the base of the additional transistor; and a second diode coupled between the base and emitter of the additional transistor wherein the effective beta of the additional transistor is reduced to reduce the bias current that would otherwise flow through the first transistor when such transistor is rendered conductive by an applied differential input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.