LSI Chip carrier with buried repairable capacitor with low inductance leads
US4453176A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1981 |
| Grant date | Jun 5, 1984 |
| Priority date | — |
| Expiry date | Dec 31, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/162
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A carrier for LSI chips includes a built-in capacitor structure in the carrier. The capacitor is located beneath the chip with the plates of the capacitor parallel to the chip mounting surface or at right angles to the chip mounting surface. The capacitor is formed by assembling an array of capacitive segments together to form the first one of the plates of a capacitor with the other plate spanning a plurality of the segments of the first plate. Each of the segments of the first plate includes a set of conductive via lines which extend up to a severable link on the chip mounting surface. The severable via is cut by means of a laser beam or the like when the capacitor must be repaired by deleting a defective segment of the capacitor. Preferably, the structure includes a pair of parallel conductive charge redistribution planes above and below the capacitor plates with connections to the respective plates providing a low inductance structure achieved by providing a current distribution which results in cancellation of magnetic flux. The lower redistribution plane is preferably connected directly to the lower capacitor plate. The upper redistribution plane is preferably connected to th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.