Extended address generating apparatus and method
US4453212A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 1981 |
| Grant date | Jun 5, 1984 |
| Priority date | — |
| Expiry date | Jul 13, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/342
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Address generating apparatus which uses narrow data paths for generating a wide logical address and which also provides for programs to access very large shared data structures outside their normally available addressing range and over an extended range of addresses. Selective indexed addressing is employed for providing index data which is also used for deriving variable dimension override data. During address generation, selected index data is added to a displacement provided by an instruction for deriving a dimension override value as well as an offset. The derived dimension override value is used to selectively access an address locating entry in a table of entries corresponding to the applicable program. The resulting accessed address locating entry is in turn used to determine the particular portion of memory against which the offset is to be applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.