Fault alignment exclusion method to prevent realignment of previously paired memory defects
US4453248A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 16, 1982 |
| Grant date | Jun 5, 1984 |
| Priority date | — |
| Expiry date | Jun 16, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for insuring that two semiconductor chips which have a 1-bit defect at the same chip address are not paired at any memory address by a fault alignment exclusion mechanism (FAEM) which functions to position chips having defects at different memory addresses. The FAEM employs an error map to determine which chips must be realigned in their respective columns and an address permute vector functions to effectively change the physical address of the chip in the column to a logical address. The two permute vectors for the two columns contributing to any uncorrectable error are "exclusive-ORed" and the result stored in a second map along with an identification of the chip columns. Any time in the future that a new permute vector is proposed for assignment to any column of chips, the changed permute vector is exclusive-ORed with the permute vectors currently assigned to all other columns of the memory to see if any such combination produces a result forbidden by the forbidden result table. If no such forbidden result is found, the proposed permute vector can be assigned with the assurance that no pair of chips previously found to produce aligned faults will align now …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.