Fabrication of FETs
US4453306A · kind A · utility
30Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 1983 |
| Grant date | Jun 12, 1984 |
| Priority date | — |
| Expiry date | May 27, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a layer such as palladium over the gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon and palladium form a silicide which is then selectively etched leaving the remaining polycrystalline silicon aligned with the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.