Parallel cyclic redundancy checking circuit
US4454600A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 1982 |
| Grant date | Jun 12, 1984 |
| Priority date | — |
| Expiry date | Aug 25, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/01
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A parallel cyclic redundancy checking circuit which determines the validity of digital, binary, cyclical data. The parallel structure of this circuit enables it to check high frequency data. Shift registers store sequentially occurring parallel groups of data and a feedback network comprising exclusive-or gates provides a coding arrangement which produces a resultant data pattern to indicate the validity of the cyclical parallel input data. Resultant data patterns are periodically stored in a random-access-memory which initializes the shift registers to provide a time sharing operation. A comparator detects invalid data by comparing the resultant patterns with expected values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.