Digital supervisory circuit for a telephone system
US4455456A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 1982 |
| Grant date | Jun 19, 1984 |
| Priority date | — |
| Expiry date | Apr 26, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M19/026
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The digital supervisory circuit comprises an amplitude comparator and EXCLUSIVE-OR gate to provide an output signal indicating the difference in time an input signal is above and below a predetermined reference potential. This output signal is integrated in an up-down binary counter and also is coupled to a first logic circuit under control of the counter which provides a ring present supervisory signal when a first threshold is exceeded and a second logic circuit under control of the counter which provides a switch hook detection supervisory signal when a second threshold is exceeded. A hit-timing circuit is provided coupled to the counter and the first and second logic circuits to prevent response of the counter and second logic circuit to line transients.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.