Logic control system for efficient memory to CPU transfers
US4455606A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1981 |
| Grant date | Jun 19, 1984 |
| Priority date | — |
| Expiry date | Sep 16, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.