Random access memory cell
US4455625A · kind A · utility
2Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 1983 |
| Grant date | Jun 19, 1984 |
| Priority date | — |
| Expiry date | Jan 17, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Two memory cells each can be entirely fabricated in only two isolation beds. In one embodiment each bed contains one lateral PNP and one vertical NPN transistor in a merged structure. To obtain faster switching speeds, the PNP transistors are cross-coupled as flip-flop transistors while the NPN transistors act as load transistors. A word select signal is applied to forward bias the base-emitter junctions of the NPN load transistors, to thereby generate a potential difference between bit lines coupled to the emitters of the PNP flip-flop transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.