Real time fault tolerant error correction mechanism
US4455655A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1981 |
| Grant date | Jun 19, 1984 |
| Priority date | — |
| Expiry date | Sep 28, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2020/10916
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a real-time fault-tolerant hardware error correction device which is typically implemented as a data transfer circuit between a disc memory and a processing unit. It operates in two modes: as an encoding system and error detector on a disc write, and as a decoding system and error corrector on a disc read. In its first mode, each block of data from the processing unit is encoded with an error syndrome as it is transmitted to the disc memory. Two identical linear feedback shift registers (LFSR's) are used for error detection purposes. In its second mode, the same two LFSR's are implemented with a buffer memory to achieve real-time error correction. Data flow to the LFSR's from the disc memory is alternated block-by-block, one block being received by one LFSR and the succeeding block being received by the other LFSR. At the same time that data is channeled to a particular LFSR, it is channeled synchronously to the buffer memory. While one LFSR is decoding the incoming block, the other LFSR is providing output signals to correct the previous data block which is leaving the buffer memory as new incoming data arrives.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.