Data processing system having redundant control processors for fault detection
US4456952A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 6, 1980 |
| Grant date | Jun 26, 1984 |
| Priority date | — |
| Expiry date | Nov 6, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system including a control store for storing a microprogram constituted by a number of microinstructions, first and second control processors connected in dual fashion for processing data at the same time under control of the microprogram and a cache memory for storing a part of data stored in a main memory. The system compares micro-addresses from the first and second control processors and combines the micro-addresses to form one micro-address and supplies the micro-address to the control store. The system includes an input circuit for simultaneously supplying to the first and second control processors a micro-instruction which the control store reads out upon receipt of said micro-address from the micro-address comparator, and a CPU-to-cache interface comparator including a second comparator circuit for comparing memory-addresses given from the first and second control processors, and then combines these memory-addresses to form one memory address and supplies the memory-address to the cache memory. The first and second control processors are simultaneously supplied with an operand which the cache memory reads out upon receipt of the memory-address from the CPU…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.