Apparatus for high speed fault mapping of large memories
US4456995A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1981 |
| Grant date | Jun 26, 1984 |
| Priority date | — |
| Expiry date | Dec 18, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/079
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus is disclosed for mapping and classifying the faulty bits of a large computer memory. Known data is read into the memory (1) and then the data stored in the memory is read out in a predetermined sequence (17, 18). The data read out is compared (10) with the known written data and the mismatches (errors) are counted (11, 12). Based upon the number of errors counted and the known sequence in which the stored data is read out, the type of fault is determined, e.g., a failure of an entire bit line, a failure of an entire word line, etc., and a status byte is established (7) representing the fault type. The status byte is useful in determining a reconfiguration of the memory whereby the faulty memory bits are scattered among accessed data words in such a way that available error correcting capability can correct the remaining faulty bits in each data word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.