Universal interconnection substrate
US4458297A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 29, 1982 |
| Grant date | Jul 3, 1984 |
| Priority date | — |
| Expiry date | Nov 29, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/0298
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a wafer substrate for integrated circuits (1) which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal (19, 20), thus providing two principal levels of interconnection. An insulation layer (21) is placed between the metal layers and also between the lower metal layer and the substrate if the latter is conductive. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layer or layers, respectively. The real estate provided by the substrate (1) is divided up into special areas used for inner cells (2) outer cells (3) signal hookup areas (4) and power hookup areas (5). The cells are intended to host the integrated circuit chips (24, 25) and to provide the bonding pads (8) for the signal connections between the chips and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.