Microprocessor controlled communications controller having a stretched clock cycle
US4458308A · kind A · utility
26Cited by
19References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1980 |
| Grant date | Jul 3, 1984 |
| Priority date | — |
| Expiry date | Oct 6, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A communications controller of a data processing system uses a microprocessor to control communication operations. Apparatus in the controller stretches the microprocessor clock cycle signals for selected operations to allow the microprocessor speed to match the speed of the logic performing the selected operation. The apparatus includes a counter which is freerunning for the stretched cycle and reset on a predetermined cycle for the "no stretch" cycle. A decoder coupled to the counter conditions logic gates to generate the microprocessor clock cycle signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.