Integrated injection logic semiconductor devices

US4459606A · kind A · utility

Assignee

• Tokyo Shibaura Electric · JP

Inventors

• Yukuya Tokumaru · Yokohama, JP
• Masanori Nakai · Yokohama, JP
• Satoshi Shinozaki · Yokohama, JP
• Junichi Nakamura · Settsu, JP
• Shintaro Ito · Tokyo, JP
• Yoshio Nishi · Palo Alto, US

Key dates

• Filing date: Dec 24, 1975
• Grant date: Jul 10, 1984
• Expiry date: Dec 24, 1995

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/211

Abstract

The integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on the N type semiconductor substrate, a first N type region extending through the P type semiconductor layer to reach the N type semiconductor substrate, a P type region formed in the first N type region and having a periphery along the outer periphery of the first N type region and a second N type region formed in the P type semiconductor layer. The integrated injection logic semiconductor device is constituted by a PNP lateral transistor utilizing the P type region, the first N type region and the P type semiconductor layer as the emitter, base and collector electrodes respectively, and a NPN vertical transistor utilizing the N type semiconductor substrate, P type semiconductor layer and the second N type region as the emitter, base and collector electrodes, respectively.