Microcomputer with automatic refresh of on-chip dynamic RAM transparent to CPU
US4459660A · kind A · utility
24Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1981 |
| Grant date | Jul 10, 1984 |
| Priority date | — |
| Expiry date | Apr 13, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microcomputer device is disclosed containing a ROM for program memory, a read/write memory, and a CPU in a single integrated circuit. Input/output ports, interrupt and operating mode controls are memory mapped in the same logical address space as the program and read/write memory. The read/write memory is an array of one-transistor type dynamic storage cells in which data bits are stored in capacitor; refresh of this dynamic RAM is accomplished in a manner transparent to the CPU by an automatically-incremented address counter. Each data bit uses two one-transistor cells in a balanced, complementary array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.