Integrated circuit having a multi-layer interconnection structure
US4459687A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1982 |
| Grant date | Jul 10, 1984 |
| Priority date | — |
| Expiry date | Apr 2, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a multi-layer interconnection structure comprises a logic section of series-connected MOS FETs each having a gate input connection layer made of a polysilicon layer on a semiconductor substrate of one conductivity type and source and drain semiconductor regions of the other conductivity type formed in the surface of the substrate along such a direction as to traverse the gate input connection layer, a load device connected to one end of the logic section, and interconnection structure for causing a signal, at a junction of the load device and logic the section, to be transmitted to the other end of the logic section across the gate input connection layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.