Self-pacing serial keyboard interface for data processing system
US4460957A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1981 |
| Grant date | Jul 17, 1984 |
| Priority date | — |
| Expiry date | Aug 12, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial keyboard interface (28) connects a self scanning programmable serialized keyboard (40) to the system bus (10) of a data processing system. A cable (42) containing only a clock wire (52) and a data wire (58) provides the connection. The keyboard transmits a 9-bit scan out code consisting of a start bit followed by eight serial data bits. The keyboard clock line (52) is connected to the clock or shift terminal of a serial-to-parallel shift register encoder (62) for shifting the data bits on data line (58) into the encoder which has eight parallel output data lines (A, B . . . G, H) connected to the system bus. When the encoder (62) contains a complete scan out frame, the start bit is in the most significant stage (h') and sets the D-type latch (68) to apply a CPU interrupt request to the system bus (10). At this time, the Q output of latch (68) pulls down the data line to ground potential, thereby disabling the data line and preventing further keyboard transmission of data. When the interrupt request is granted by the CPU, a clear signal resets latch (68) to remove ground potential from data line (58) and thereby permit further transmission of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.