Logic control system including cache memory for CPU-memory transfers
US4460959A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1981 |
| Grant date | Jul 17, 1984 |
| Priority date | — |
| Expiry date | Sep 16, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.