Method for preparing an insulated gate field effect transistor
US4461072A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1983 |
| Grant date | Jul 24, 1984 |
| Priority date | — |
| Expiry date | May 20, 2003 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/973
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed here is an IGFET formed on the single crystal silicon substrate where the major plane surface is deviated within the range from 22 degree to 34 degree toward the crystallographic surface {1,1,1} from {1,0,0} or on the silicon epitaxial layer formed on said substrate. Here, generation of silicon nitride is suppressed, which is newly formed under the mask in the selective oxidation process using the silicon nitride as the mask and also is the main cause of lowering the breakdown voltage of the gate insulating film. In addition, various kinds of functional characteristics depending on the crystallographic surface orientation are not interfered at all. Thereby, the present invention can offer an IGFET which drastically improved the breakdown voltage failure rate of the gate insulating film while keeping the functional characteristics at the best condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.