High speed CMOS sense amplifier
US4461965A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 1980 |
| Grant date | Jul 24, 1984 |
| Priority date | — |
| Expiry date | Aug 18, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pair of CMOS inverters are cross coupled in a latching configuration. Both inverter supply terminals are coupled to complementary toggles that can render the inverters operative or inoperative. First, the inverters are rendered inoperative. An output switch is coupled between the output nodes so that the inverter's output nodes can be driven to the same potential, thus canceling any offset voltage. An input switch produces sampling over a time interval that extends beyond the output switch on period. After the sampling period, the toggles are operated to turn the inverters on and to produce a latch state determined by the potential change present in the sampling interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.