Word group redundancy scheme
US4462091A · kind A · utility
5Cited by
1References
7Claims
0Family size
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Key dates
| Filing date | Feb 26, 1982 |
| Grant date | Jul 24, 1984 |
| Priority date | — |
| Expiry date | Feb 26, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/781
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A word redundancy scheme for a high speed RAM where the bit output stage uses on-chip logic. An extra emitter on each of the decoders is utilized including redundant word group decoders. A compare circuit has an output to each of the extra emitters and when the address of a bad bit arrives at the compare circuit it de-selects each of the non-redundant decoders at that address and selects the redundant decoders via the extra emitters. Hence, the redundant decoders replace the decoders of the bad bit position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.