Serial/parallel input/output bus for microprocessor system
US4463421A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 1983 |
| Grant date | Jul 31, 1984 |
| Priority date | — |
| Expiry date | Jul 26, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. For a given set of addresses parallel data transfers occur and for a different set of addresses serial data transfers occur. A single instruction may transfer one bit, multiple bits in series, or bytes or words in parallel; the serial or parallel mode is specified by the address, so software may be written without regard for the type of interface. This serial/parallel I/O port shares the address/data bus with memory and may be used with any memory-mapped peripheral.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.