Squaring circuit bypass
US4464586A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 10, 1982 |
| Grant date | Aug 7, 1984 |
| Priority date | — |
| Expiry date | May 10, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital signal bypass circuit including a two terminal clock input for supplying a clock input signal with a predetermined first frequency. A divide-by-two squaring circuit is also provided which is input for synchronously translating the clock input signal into an output signal having a frequency one-half of the predetermined first frequency. A bypass circuit is provided which is connected to the clock input and responsive to the clock input signal applied thereto, the bypass circuit being operative to disable the divide-by-two squaring circuit so that the output signal has a frequency equal to the predetermined first frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.