Circuit for trimming FET differential pair offset voltage without increasing the offset voltage temperature coefficient
US4464631A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 1, 1981 |
| Grant date | Aug 7, 1984 |
| Priority date | — |
| Expiry date | Dec 1, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45696
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for trimming the offset voltage of a differential amplifier is provided comprising a pair of FET input transistors forming an input stage to the amplifier, and an offset adjustment circuit comprising a temperature-dependent resistive network for reducing post-trim offset voltage drift. The offset voltage is a function of a mismatch between the drain-to-source currents of the inputs transistors. The offset adjustment circuit provides for initial trimming of the offset voltage and automatic post-trim reduction of drift by decreasing this drain-to-source current mismatch to track the decrease in non-controllable device mismatch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.