Binary MOS carry-look-ahead parallel adder
US4464729A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 14, 1981 |
| Grant date | Aug 7, 1984 |
| Priority date | — |
| Expiry date | Oct 14, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Unlike prior art parallel adders, which employ conventional EXCLUSIVE-OR gates, the parallel adder disclosed uses special EXCLUSIVE-NOR gates constructed from only three transistors, so that a considerable space-saving and a reduction of power dissipation are achieved on the integrated-circuit chip. Instead of noninverted digit signals, inverted digit signals are used to form the E and D signals which are combined by means of a complex gate for each binary weight to form the inverted carry signal of this weight. This complex gate includes a number of AND elements equal to the number of the stage, and a NOR element combining the outputs of these AND elements and the D signal of this stage. The inverted carry signal of a stage and the inverted subtotal signal of the next higher-order stage are combined by means of an EXCLUSIVE-NOR gate of the above-mentioned special circuit construction to form the noninverted sum signal of the next higher order stage. The inverted subtotal signal of each stage is also provided by an EXCLUSIVE-NOR gate of the above-mentioned special circuit construction combining the E and D signals of that stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.