Dynamic synchronous binary counter with stages of identical design

US4464773A · kind A · utility

Assignee

• ITT Industries · US

Inventors

• Reiner Backes · Glückstadt, DE
• Friedrich Schmidtpott · Hartheim, DE
• Mathew Neal · Glückstadt, DE

Key dates

• Filing date: May 21, 1982
• Grant date: Aug 7, 1984
• Expiry date: May 21, 2002

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K23/44
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A first variant using conventional ratio-type two-phase design with nonoverlapping clock signals consists of a first inverter (I1), a complex gate (KG), a first transfer transistor (T1), a second inverter (I2), and a third inverter (I3) connected in series with respect to the signal flow. The complex gate (KG) consists of two NORed AND elements (U1, U2). The output of the second inverter (I2) is the count-up output (VA), and that of the third inverter (I3) is the count-down output (RA). The count-up output (VA) is coupled through a second transfer transistor (T3), controlled by the second clock signal (F2), to the first input of the first AND element (U1), whose second input is connected to the output of the first inverter (I1). The count-down output (RA) is coupled through a third transfer transistor (T2), controlled by the second clock signal (F2), to the first input of the second AND element (U2), whose second input is connected to the output of the NOR gate (NG) through a fourth transfer transistor (T 5), which is also controlled by the second clock signal (F2). One of the two inputs of the NOR gate is connected to the carry input (UE) in each stage. The carry input (UE) is con…