Three state input circuits
US4465944A · kind A · utility
11Cited by
2References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 7, 1982 |
| Grant date | Aug 14, 1984 |
| Priority date | — |
| Expiry date | Jan 7, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The three state input circuit includes a P channel MOS FET and an N channel MOS FET which are supplied with an input signal at their drain electrodes, and a pair of flip-flop circuits connected to source electrodes of respective FETS and acting as a memory. Gate electrodes of the FETs are supplied with timing signals. The circuit operates to sequentially and periodically judge the input states in accordance with the timing signals, and then the stores results of such judgements and then outputs the stored results as 2 bit binary signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.