Information processing system including a one-chip arithmetic control unit
US4466055A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1981 |
| Grant date | Aug 14, 1984 |
| Priority date | — |
| Expiry date | Mar 17, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an information processing system in which an arithmetic control unit is formed on one chip by very large scale integration and is connected to external devices by a common bus, microinstructions from an externally-connected control memory, memory information output from an external main memory and information output from I/O devices, can be received by the arithmetic control unit on the common bus. An external setting signal for selecting whether the instruction system of the arithmetic control unit is to be enabled or disabled is input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction. A bus width setting signal from an I/O device is also input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction, and the CPU determines whether the data width of an I/O device is 8 bits or 16 bits. An interruption signal from an I/O device and a signal indicating an abnormal condition of a power source, for example, may be input to the arithmetic control unit from external devices on the common bus as part of a group of external signals occupying only a portion of the common bus simultaneousl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.