Wafer scale integrated circuit
US4467400A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 13, 1982 |
| Grant date | Aug 21, 1984 |
| Priority date | — |
| Expiry date | May 13, 2002 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/923
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1 is a network 11' interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12' exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.