Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories
US4467414A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1981 |
| Grant date | Aug 21, 1984 |
| Priority date | — |
| Expiry date | Aug 19, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a cache memory arrangement used between a control processor (21) and a main memory (22) and comprising operand and instruction cache memories (31, 32), a cache buffer circuit (40) is responsive to storage requests from the central processor to individually memorize the accompanying storage data and store address data and to produce the memorized storage data and store address data as buffer output data and buffer output address data together with a buffer store request. Responsive to the buffer store request, first and second cache control circuits (36, 37) transfer for accompanying buffer output address data to the operand and the instruction cache memories, if each of the operand and the instruction cache memories is not supplied with any readout requests. Preferably, first and second coincidence circuits (51, 52) are coupled to the cache buffer circuit and responsive to the readout requests to compare all of the memorized store address data with the accompanying readout address data and to make the first and the second cache control circuits preferentially process the buffer store request prior to each of the readout requests. The buffer circuit may comprise two pairs of buff…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.