Input/output buffer circuitry
US4468753A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 21, 1981 |
| Grant date | Aug 28, 1984 |
| Priority date | — |
| Expiry date | Sep 21, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input/output bus structure for a computer system is disclosed in which the computer's central processor is fully protected from "foreign" I/O devices in that all of the incoming and outgoing bus signals are buffered and the buffer stores can be disabled under software control. To attach an input/output device on the input/output bus, certain requirements, both hardware and software, must be met. The input/output bus is enabled by writing a predetermined bit pattern to a preselected output port. In response to the bit pattern, hardware in the input/output port enables the input/output bus tranceivers to receive and send information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.