Process for making CMOS field-effect transistors with self-aligned guard rings utilizing special masking and ion implantation
US4468852A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 1983 |
| Grant date | Sep 4, 1984 |
| Priority date | — |
| Expiry date | Apr 5, 2003 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/07
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Two patches of silicon nitride are formed above spaced-apart regions of an n-type substrate (2) on an overlying oxide layer (8) of small thickness. Arsenic ions are then implanted through the oxide layer in substrate areas not covered by the patches whereupon one patch (10a) and an adjoining portion of the oxide layer are covered by a masking layer (15) of polycrystalline silicon, leaving unprotected the second patch (10b) and an oxide portion adjacent thereto. The wafer is then bombarded with boron ions, first at a relatively low concentration and high energy level to penetrate the oxide layer as well as the second patch (10b) and then, after an intervening high-temperature heat treatment in a nonoxidizing atmosphere, at a relatively high concentration and low energy level. This results in the formation of a p-well (17) bounded by an n+ guard zone (23) and partly underreaching same, with an exposed area of that guard zone converted to p+ conductivity by the second-stage boron bombardment. A further heat treatment, at a somewhat lower temperature, expands the p+ area into a channel stop (21) of this conductivity type which bounds the p-well (17) but does not significantly encroach …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.