Synchronizer circuit
US4469964A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1981 |
| Grant date | Sep 4, 1984 |
| Priority date | — |
| Expiry date | Jul 20, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital synchronizer includes a latch connected to a level sensitive circuit. The latch is constructed to provide a rapid transition between logic "0" and logic "1". In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from logic "0" to logic "1" when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit. The second latch is a two inverter latch with refresh for 3/4 of a machine cycle to allow any transients conditions within the latch to dampen out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.