Process for making complementary transistors by sequential implantations using oxidation barrier masking layer
US4470191A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1982 |
| Grant date | Sep 11, 1984 |
| Priority date | — |
| Expiry date | Dec 9, 2002 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.