Transistor circuit for reducing gate leakage current in a JFET
US4472648A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 1981 |
| Grant date | Sep 18, 1984 |
| Priority date | — |
| Expiry date | Aug 25, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transistor circuit is provided comprising a primary JFET whose gate leakage current is required to be minimized, and a reference current generator means connected to the source of the primary JFET for deriving a drain-to-source current to be applied to the source of the primary JFET. The drain-to-source current has a value which forces the gate leakage current to be minimized. The reference current generator means comprises either a trimmed adjustable current source, a current source JFET, or a scaled reference source. These current devices are connected to the source of the primary JFET either directly or through a current mirror means to minimize the gate leakage current of the primary JFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.