Circuit for reproducing and demodulating modulated digital signals
US4472686A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1981 |
| Grant date | Sep 18, 1984 |
| Priority date | — |
| Expiry date | Oct 13, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/042
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for reproducing and demodulating a modulated digital signal which is modulated in a predetermined modulation system such as MFM, EFM and so on. A phase of a clock having a frequency multiplied by an integral number of a bit frequency of the modulated digital signal, is restricted or controlled by a signal showing that a predetermined pattern of the modulated digital signal occurred. The modulated digital signal is demodulated by the thus restricted clock to produce digital informations "0" and "1". A main requirement for detecting the predetermined pattern of the modulated digital signal, is that a reproduced modulated digital signal is reliable. In order to compensate for the drop-out of the modulated digital signal, the demodulation circuit is provided with a modulated digital signal reproducing circuit for complementing a predetermined signal pattern when the drop-out occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.