Instruction decoding logic system
US4472773A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1981 |
| Grant date | Sep 18, 1984 |
| Priority date | — |
| Expiry date | Sep 16, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.