Memory system with error storage
US4472805A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1982 |
| Grant date | Sep 18, 1984 |
| Priority date | — |
| Expiry date | Mar 26, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system stores bits which are read-out internally a word at a time and from which one or more bits may be selected for external read-out. Each time a bit is written into the memory the parity of the word into which the bit is written is checked and a parity bit generated and stored for the word. The parity of the words originally read internally from the memory is checked and any parity errors detected are stored as error signals. Each time a word subsequently is read internally from the memory, if there is stored for that word an error signal, and if it is also determined that the bit selected from that word for external read-out is in error, that bit automatically is corrected even if the parity of the word is found to be correct.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.