Clamping video signals
US4473846A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 1982 |
| Grant date | Sep 25, 1984 |
| Priority date | — |
| Expiry date | Aug 12, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/185
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video signal clamping circuit comprises a summing circuit (R1, R2, R9, 2) an analogue to digital converter (3), a programmable read only memory (6), a latch (7), a digital to analogue converter (9) and an integrator (11). The PROM (6) is addressed by the ADC(3) and produces a 4 bit output code which is dependent on the amplitude of the video signal. This is stored on the latch (7) and passed to the DAC(9) during a timing pulse applied to terminal (8) which occurs during the line blanking period. The DAC(9) produces an output which is stored on the capacitor (C1) in the integrator (11). The integrator (11) output is summed with the input video signal to clamp the video signal level to the reference voltage so that a clamped digital video signal is available from the output (5).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.