Dynamic replacement of defective memory words
US4475194A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1982 |
| Grant date | Oct 2, 1984 |
| Priority date | — |
| Expiry date | Mar 30, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single error correcting memory is constructed from partially good components on the design assumption that the components are all-good. Those small number of logical lines containing double-bit errors are replaced when detected with good lines selected from a replacement area of the memory. The replacement area is provided by a flexibly dynamically deallocated portion of the main memory so that it can be selected from any section of the original memory by inserting the appropriate page address in the replacement-page register. With such a memory architecture until the first double-bit error is detected (either in testing or actual use) all pages may be used for normal data storage. When such an error is detected some temporarily unused page in the memory is deal-located, that is rendered unavailable for normal storage, and dedicated to providing substitute lines. The same procedure is followed for subsequent faults. If the replacement area itself becomes defective, a different page may be chosen to provide substitute lines simply by providing a different address in the replacement page register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.