High voltage bubble memory pulse generator output stage
US4476429A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1982 |
| Grant date | Oct 9, 1984 |
| Priority date | — |
| Expiry date | Aug 27, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/64
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for providing the gate of a bubble memory with a precision current pulse at a high voltage is manufactured using a low voltage process; i.e. BV.sub.ceo is approximately 18 volts. In order to accomplish this, first and second voltage level shifting stages are cascoded and the output transistors thereof are used as Zener level shifters each level shifting downward by a BV.sub.ceo when only a small voltage is dropped across the load. If the voltage drop across the load increases, the cascoded output transistors may enter their active region and are prevented from going into saturation by saturation clamps so as to not introduce unwanted delays in the rise or fall times of the current pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.