Dual threshold decoder for convolutional self-orthogonal codes
US4476458A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 1982 |
| Grant date | Oct 9, 1984 |
| Priority date | — |
| Expiry date | Jun 14, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/43
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a decoder (10) for convolutional self-orthogonal codes which includes a multistage syndrome register (16) and is responsive to two separate threshold levels. The first threshold level, as in prior art arrangements, includes a first majority logic circuit (24) connected to selected stages of the syndrome register and functions to correct the information bits (X.sub.1 -X.sub.7) currently being processed. Instead of also using this majority logic circuit to correct the syndrome register, as in the prior art, the present invention includes a second majority logic circuit (28), which operates at a different threshold level than the first and functions to correct the selected stages of the multistage syndrome register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.